Computer systems typically require a memory system for storing information. The memory system includes a collection of storage locations. Each storage location has a physical address. The collection of storage locations form an address space for the memory system. The address space for a memory system might span a number of memory devices.
One way to access the address space of a memory system is to use logical addresses. Logical addresses are a conceptual organization of the storage locations as opposed to the physical organization of the storage locations. The logical addresses are used by the computer system to access the memory system. Logical addresses must be translated or mapped by addressing circuitry to physical addresses in order to access the actual storage locations.
One type of memory device is a semiconductor memory. Semiconductor memories generally include one or more arrays of memory cells. The arrays include rows and columns of memory cells. Each cell can store one or more bits of information. Logical addresses are typically mapped to physical addresses in semiconductor memories such that sequential logical addresses are mapped into the rows and columns of the array by a linear method or an algorithm such as the Gray code. In other words, present memory architectures tend to map logically sequential addresses to physical addresses corresponding to memory cells along the same row or column or within a very few cells of each other.
One or more memory cells of the semiconductor memory may prove to be defective. A single point defect refers to an isolated defective cell within the array. Single point defects are often correctable through software or hardware correction techniques. A number of single point defects, however, can overwhelm the abilities of the correction algorithms to recover the stored data. If a defect occurs such that a substantial number of cells in a given column prove to be defective, such a defect may be called a column defect. Similarly, if a defect occurs such that a substantial number of cells in a given row prove to be defective, such a defect may be called a row defect. Another type of defect is an area defect. In an area defect, typically a number of adjacent cells, possibly spanning multiple rows or columns, prove to be defective. Non-catastrophic defects might be accounted for using error correction algorithms implemented in hardware or software. Catastrophic defects can not be accounted for and might be so substantial as to render entire rows, columns, or even the entire memory device useless.
When retrieving information from a memory system, computers tend to access groups of logically sequential addresses. In other words, related information tends to be clustered together such that the information is retrieved from groups of sequential logical addresses. One example is a burst read memory access. In a burst read access, a starting location and a number of logically sequential memory locations to be read are provided by the computer system. The addressing circuitry starts at the starting location and accesses logically sequential memory locations until the requisite number of memory locations has been read. Thus for a memory with row or column defects, addressing circuitry which uses the prior art logical-to-physical address mapping scheme is likely to access a number of point defects and is particularly susceptible to defects that generate row or column errors for a given burst mode read.
Examples of burst read applications include emulation of a disk drive storage system or transferring information between disk drive storage systems and other storage devices. In a disk drive system, data is typically stored and transferred in block units often referred to as sectors. Although sector size may vary, a typical sector size might be 512 bytes so that transfers to and from a disk drive occur in integer multiples of 512 bytes of data. Thus a burst read access might be used to access one or more sector's worth of data from the semiconductor memory.
Error detection and correction (EDAC) software might be uses to correct errors due to the defective cells. Currently EDAC is capable of correcting single or double bit errors in a single 512 byte burst. This could present problems for using EDAC to correct for row, column, and area failures because present memory architectures tend to read across full rows or adjacent rows or along the same column which in turn tend to have higher bit error rates. The higher bit error rates may exceed the capability of the error correction algorithms such that the entire burst read is considered defective due to the excessive bit error rate.
Thus one disadvantage of the prior art mapping scheme is the susceptibility to row, column, or area defects which cannot be corrected through error correction algorithms.
One method of correcting for row or column errors has used row or column redundancy during the fabrication process. The semiconductor memory is fabricated with an excess number of rows and columns of memory cells. The addressing circuitry remaps the rows or columns so that the redundant rows or columns are substituted for the defective rows or columns. Such remapping tends, however, to be ineffective for area defects unless there are a sufficient number of available redundant rows and columns. Furthermore, even if rows and columns are remapped due to area defects, all the non-defective cells in the columns and rows spanned by the area defect are no longer available for storage because the entire row or column has been replaced with a redundant row or column, respectively.
In addition, the defects within the memory device may be so numerous and distributed in such a manner so as to result in catastrophic failures for a substantial number of block reads. If the number of catastrophic failures exceeds a certain threshold, the memory device may not even be marketable and thus will need to be scrapped.
Thus another disadvantage of the prior art mapping scheme is that production yield for the memory devices is particularly sensitive to the physical distribution of the defects within the memory device.